In semiconductor devices including DRAMs (Dynamic Random Access Memories), write data is held in a memory cell array in which memory cells are arranged. Further, the semiconductor devices include sense amplifiers each for amplifying data read from a memory cell to a level that can be handled as a digital signal.
A demand such as chip size reduction is constantly present for the semiconductor devices.
Patent Document 1 discloses a DRAM having a multi-bank configuration capable of transferring data at high speed without causing an increase in chip size due to an increase in power supply interconnect width or addition of an internal power supply circuit. Patent Document 1 discloses that the width of a power supply interconnect needs to be wider than the width of a signal interconnect to transfer a signal, and that, in view of the width of the power supply interconnect, reduction of the number of power supply interconnects strongly influences reduction of the chip size.
Further, Patent Document 2 discloses a technique of setting a target potential of a sense amplifier to an array voltage VARY and accelerating a sense operation by using a voltage (overdrive voltage, VOD) that is higher than the array voltage VARY.
FIG. 2 is a diagram showing an example of an overdrive circuit used for each sense amplifier. Reference characters VDDSA and VSSA shown in FIG. 2 denote power supplies to be used when the sense amplifier amplifies data from a memory cell, and reference character VOD/VARY indicates a voltage to be supplied to the power supply VDDSA. By appropriately controlling each of control signals (VOD_ACT, VARY_ACT, and VSS_ACT) in FIG. 2, the voltage VOD which is higher than the voltage VARY is supplied to the power supply VDDSA at a beginning of a charging period. As a result, a period of time for charging from a precharge level to the voltage VARY can be reduced.